There is an increasing demand for semiconductor memories that can be electrically erased and programmed without the need for refreshing data stored in the memory. Also, there is a trend toward enhancing the storage capacity and the density of integration in memory devices. NAND-type flash memory is one example of a nonvolatile semiconductor memory that provides high capacity and integration density without the need for refreshing stored data.
FIG. 1 contains a block diagram of an array of memory cells and page buffers assigned to the array in a NAND-type flash memory. The memory includes a cell array 10, row decoder 20, page buffer group 30 and Y-pass gate circuit 40. Cell array 10 is formed of a plurality of strings 12 (a "string" is a cell unit corresponding to one bit of data) arranged in columns. Each string includes a string selection transistor SSTm (m=0,1,2, . . . ,I), the gate of which is coupled to a string selection line SSL. Each string also includes a ground selection transistor GSTm (m=0,1,2, . . . ,I), the gate of which is coupled to a ground selection line GSL. Memory cells MCj are connected in series between each string selection transistor SSTm and its associated ground selection transistor GSTm. Control gates of the memory cells are coupled to word lines WLj. The drain of each string selection transistor SSTm is connected to its corresponding bit line BLm, and the source of each ground selection transistor GSTm is connected to a common source line CSL. Outputs of row decoder 20 are connected to SSL, CSL and word lines WL0-WLm.
The page buffer group 30 includes page buffers 30.sub.-- m corresponding to the bit lines BLi. During a read cycle, a page buffer senses data from a selected memory cell and then transfers the data to a data output buffer through Y-pass gate circuit 40. During a write cycle, a page buffer stores data applied from a data input buffer through Y-pass gate circuit 40. Hereinafter, even page buffer 30.sub.-- 0, corresponding to bit line BL0, is referred to in describing the read and write operations. Other page buffers 30.sub.-- 1-30.sub.-- i, corresponding to other bit lines BL1-BLi, have the same constructions and functions as those of the 30.sub.-- 0.
Page buffer 30.sub.-- 0 includes PMOS transistor M2, six NMOS transistors M1 and M3-M7, a latch 50 formed of inverters IV1 and IV2, and tri-state inverter IV3. NMOS transistor M1, the gate of which is coupled to signal BLSHF, is connected between node N1 and bit line BL0 to adjust a voltage level of BL0 which is developed while being activated and to prevent page buffer 30.sub.-- 0 from being influenced by a high voltage when the high voltage is applied to BL0. The gate and source of PMOS transistor M2, whose drain is connected to node N1 (the drain of M1), are connected to a signal CURMIR and a power source voltage Vcc, respectively. PMOS transistor M2 supplies current to BL0 in response to signal CURMIR. NMOS transistor M3, the source and gate of which are connected to ground Vss and signal DCB, respectively, is connected between node N1 and Vss and discharges a voltage of BL0 and resets the page buffer to a ground level. NMOS transistor M4, the gate of which is coupled to signal SBL, is connected between node N2 of latch 50 and node N1. The drain of M4 is connected to Y-pass gate circuit 40 through tri-state inverter IV3, the state of which is controlled by signals Osac and OsacB (the complement of Osac). Data to be programmed is transferred to node N2 of latch 50 through NMOS transistor M7, the gate of which is coupled to signal SPB. Node N3 (a complimentary node of N2) of latch 50 is connected to Vss through NMOS transistor M5, whose gate is coupled to node N1, and NMOS transistor M6, whose gate is coupled to signal Olatch. NMOS transistors M5 and M6 change a state of data stored in the latch in response to a voltage level on bit line BL0.
FIG. 2 contains a flow chart illustrating the logical flow of a programming operation in a memory. As shown in FIG. 2, before programming, data to be written is supplied to latch 50 and stored therein S10!. Thus, latch 50 of page buffer 30.sub.-- 0 (FIG. 1) is set to the ground potential while another latch corresponding to a program-prohibited memory cell is held in Vcc. In the programming step S20!, after setting the latch, a program voltage (Vpgm) is applied to a selected word line while a pass voltage (Vpass) is applied to unselected word lines. Then, in a memory cell coupled to the selected word line and corresponding to the latch set in Vss, electrons are injected into its floating gate, causing a threshold voltage of the cell to be increased, such that the memory cell is programmed. Memory cells corresponding to the latch set at Vcc do not experience the injecting condition, and threshold voltages of the unselected memory cells do not change. After programming, for all of the cells, the program verifying operation S30! starts with retrieving retrieval of data from the programmed cell. If the programming of the selected cell has been successfully completed, the holding state of the corresponding latch 50 may be changed from Vss to Vcc. If, however, there is at least one page buffer which has still held data regarded as Vss even after the verifying cycle, the former steps S10!, S20! and S30! are repeatedly conducted until the memory cell corresponding to the unchanged page buffer is properly programmed S40!.
FIG. 3 contains a timing diagram of signals controlling the page buffers of FIG. 1 during a programming verifying cycle, and FIG. 4 shows distribution profiles for threshold voltages of a memory cell transistor after the programming verifying cycle. With respect to the program verifying operation, referring to FIGS. 1-4, assuming that word line WL1 is selected, data "0" is loaded in the latches 50 of page buffers 30.sub.-- 0 and 30.sub.-- 1 which correspond each to BL0 and BL1, and memory cell MC1 coupled to WL1 and BL0 has been programmed with its threshold voltage about 1 V during step S20 while another memory cell MC1 coupled to WL1 and BL1 has its threshold voltage about 0.3 V after the step S20. String selection line SSL, ground selection line GSL and unselected word lines WL0 and WL2-WL15 are set to Vcc or voltages higher than Vcc while the selected word line WL1 and common source line CSL are held at 0 V, as shown in FIG. 3. Consequently, the voltage of signal BLSHF goes to a predetermined level, for instance, about 2.2 V, and signals SBL and DCB are 0 V. Signal CURMIR drops down to a predetermined voltage level. With the biasing condition with the control signals, BL0 is pulled up to about 1.5 V by NMOS transistor M1 which has a threshold voltage about 0.7 V, and BL1 is pulled down to 0 V because its corresponding memory cell has not been completely programmed as an off-cell. Therefore, node N1 of page buffer 30.sub.-- 0 and node N1' of page buffer 30.sub.-- 1 become the voltage levels of Vcc and Vss, respectively.
Thereafter, when signal Olatch goes to Vcc from 0 V, the output of the latch in page buffer 30.sub.-- 0, set1, is changed to Vcc from Vss by the NMOS transistors M6 and M14 responding to Olatch. The output of the latch in page buffer 30.sub.-- 1, set2, is still held in Vss because NMOS transistor M13, the gate of which is coupled to node N1', is turned off. Thus, since the voltage level on BL0 retains Vcc that is available to set the BL0 into a program protecting condition during the following program cycles, the memory cell assigned to BL0 can maintain the threshold voltage of 1 V without being increased even during repeated programming. Also, the memory cell under-programmed, assigned to BL1, is subjected to the following program cycles until it has the desired threshold voltage (about 1 V).
However, as the NAND-type flash memory conducts the programming operation for all of memory cells coupled to a single word line in the same time, it is virtually impossible to complete a programming operation in just a single cycle. The programming must be activated many times to program the cells. Such repeated looping increases the current passing through the memory cells, causing a voltage level on the common source line to increase. The increase of the voltage on CSL, called CSL noise, may disturb the verifying function in which an under-programmed memory cell, i.e., having a threshold voltage lower that the desired level of 1 V, could be determined to be a completely programmed cell. For example, assuming that a voltage level of CSL has been increased to about 0.7 V due to the cell current for several verifying cycles and a selected memory cell MC0 has a substantial threshold voltage of about 0.3 V at present, a detected threshold voltage of the memory cell MC0 becomes as if it is 0.7 V in a present verifying step. As a result, the output of the latch in the page buffer corresponding to the memory cell is forced to be changed to Vcc from Vss. As a result, the under-programmed cell which was considered to be a completely programmed cell, i.e., an off-cell, by the malfunction, may cause a failure for data storing in the memory device. As shown in FIG. 4, threshold voltages of some memory cells are distributed in the region lower than the criteria by which it is determined whether a memory cell is an off-cell.